The present disclosure relates generally to integrated circuits (ICs), which may include programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to determining, displaying, and/or controlling variations to a circuit design for an integrated circuit.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs) are ICs that may be highly flexible devices. FPGAs may include logic that may be programmed after manufacturing to provide functionality that the FPGA may be designed to support. Thus, FPGAs contain programmable logic, or logic blocks, that may perform a variety of functions on the FPGAs, according to a user's circuit design. Different components of a circuit design may use different respective clock signals produced by a clock generator to perform programmed functions. The frequency of each clock signal—also referred to in this disclosure as “performance,” since the frequency of each clock signal affects how quickly the circuitry that uses that clock signal may operate—may be limited by the design of the circuitry.
One technique to improve the performance of the circuit design is the use of register retiming, which moves registers back and forth across combinational logic to improve the maximum achievable clock signal frequency. However, the benefits of retiming are often limited due to the use of certain constructs in circuit designs that inadvertently inhibit retiming. Such restrictions might include user directives intended for other purposes but that also limit retiming, the use of certain hardware features, such as asynchronous clears, that might be incompatible with retiming on some architectures, or even simply the lack of sufficient available registers for retiming. Some computer aided design (CAD) tools are being developed that can remove these restrictions or add registers to demonstrate the performance potential of retiming with changes to the user's circuit design. Such changes, however, may entail tradeoffs between performance and other potentially detrimental circuit-design changes. The circuit designer may not be aware of the multitude of variations available and/or the tradeoffs that may be associated with those variations.